1. Field of the Invention
The present invention relates to a film with metal foil. More specifically, the invention relates to a film with metal foil useful for producing a circuit sheet which is used in the production of a multi-layer wiring board such as a package for containing a semiconductor element and to a film with metal foil useful for producing the multi-layer wiring board from the circuit sheet.
2. Description of the Prior Art
It is a modern trend toward producing electronic devices in ever small sizes. In these circumstances, the development of portable data terminals and the widespread use of a so-called mobile computing for executing the operation by bringing a computer, have further urged the devices to be realized in smaller sizes and the multi-layer wiring board contained in the electronic devices to be fabricated in smaller sizes and in smaller thicknesses yet forming more fine circuitry.
Further, electronic equipment that must operate at high speeds have been widely used as represented by communications equipment. In order to cope with such electronic equipment, it has been urged to provide a multi-layer printed wiring board adapted to high-speed operation. The high-speed operation involves a variety of requirements such as a correct switching operation for the signals of a high frequency. To execute the high-speed operation, it becomes necessary to shorten the length of the wirings, to decrease the width of the wirings, to decrease the gap among the wirings, and to shorten the time required for the propagation of electric signals. That is, the multi-layer wiring board must be realized in a small size, in a decreased thickness and forming a fine circuitry (highly dense circuitry) even from the standpoint of coping with a high-speed operation.
A build-up method has been known for producing a multi-layer wiring board that satisfies the above-mentioned requirements.
According to the build-up method, first, a wiring/circuit layer is formed on the surface of an insulating board made of a glass-epoxy composite material, and through-hole conductors are formed so as to be electrically joined to the wiring/circuit layer on the surface, thereby to fabricate a core board.
Next, a photosensitive resin is applied onto the surface of the core board to form an insulating layer, which is then exposed to light and is developed to form via-holes in the insulating layer.
A layer such as of copper or the like is plated on the whole surface of the insulating layer inclusive of the surfaces of the via-holes. Further, a photosensitive resist is applied onto the surface of the plated layer followed by exposure to light, developing, etching and removal of resist to form the wiring/circuit layer.
Next, as required, the insulating layer is formed and the wiring/circuit layer is formed by using the resist repetitively in order to obtain a wiring board of a multi-layer structure having a plurality of circuit boards laminated on the core board.
In recent years, further, there has been developed a build-up method in which a copper foil onto which an uncured thermosetting resin is applied is laminated on a core board, instead of laminating an insulating layer on the core board using a photosensitive resin.
That is, the copper foil is stuck onto the surface of the core board by the hot press or the like method with the uncured thermosetting resin layer sandwiched therebetween, followed by heating to cure the thermosetting resin thereby to form an insulating layer having a copper foil on the surface. Then, via-holes are formed in the copper foil and in the insulting layer by using a carbonic acid gas laser or the like laser. Then, in the same manner as the above-mentioned method, a plated layer is formed, resist is applied, exposure to light is effected, developing is effected, etching is effected and the resist is removed to form a wiring/circuit layer. Then, as required, the above-mentioned steps are repeated to obtain a wiring board having a multi-layer structure in which a plurality of circuit boards are laminated on the core board.
However, the following problems are involved when it is attempted to produce the multi-layer wiring board relying upon the above-mentioned build-up method.
A first problem is that the resin constituting an insulating layer laminated on the core board loses characteristics. That is, according to the above build-up method, a photosensitive epoxy resin is generally used for forming an insulating layer. The epoxy resin, however, has a low glass transition point and further has photosensitive property. When the multi-layer wiring board obtained by this method is left to stand, therefore, the coefficient of water absorption increases. When left to stand under high-temperature and high-humidity conditions, in particular, the multi-layer wiring board loses insulating property and, hence, loses reliability of the circuit.
A second problem is that the circuit is not intimately adhered. According to the above-mentioned build-up method in which the wiring/circuit layer is formed on the insulting layer by the plating method, in particular, the adhesive strength is small between the wiring/circuit layer and the insulating layer. When, for example, the obtained multi-layer wiring board is heated by solder reflow or the like, the wiring/circuit layer is peeled off or swells.
A third problem is that the obtained multi-layer wiring board lacks surface smoothness. For example, according to the former build-up method for forming the insulating layer by applying the photosensitive resin, the photosensitive resin is in a liquid form. Accordingly, ruggedness in the surface of the core board is reflected up to the surface of the multi-layer wiring board that is built up to form ruggedness. It is expected that directly connecting a silicon chip such as flip chip on the surface of the multi-layer wiring board will become a main stream of mounting the silicon chips in the future. However, the flip chip mounting requires a high degree of flatness on the surface of the board, and the board having a rugged surface as described above does not permit the silicon chips to be mounted.
The latter build-up method that uses a copper foil onto which a half-cured thermosetting resin is applied, is superior to the former build-up method that involves the above-mentioned first and second problems. However, the wiring/circuit layer formed on the surface of the insulating layer is protruding beyond the surface of the insulating layer still involving the third problem which is concerned with the surface flatness.
Besides, according to the latter build-up method, the wiring/circuit layer is formed by plating copper on the surface of the copper foil. Therefore, the wiring/circuit layer is thick making it difficult to form a highly dense and fine wiring/circuit layer. Accordingly, improvements are required such as decreasing the thickness of the copper foil by half-etching.